Integrated Circuit (IC) devices typically include numerous transistors that are fabricated on, for example, silicon wafers. There are several types of IC devices, including Application Specific Integrated Circuit (ASIC) devices and Programmable Logic Devices (PLDs). ASIC devices have internal circuitry including logic elements connected by dedicated (hard-wired) interconnect lines such that each ASIC device performs a predetermined (fixed) logic operation. ASIC devices also have dedicated input pins for receiving input signals from other devices, and dedicated output pins (terminals) for transmitting output signals to other devices. In contrast to ASIC devices, PLDs have internal circuitry including undedicated (user-configurable) logic elements and interconnect resources that are programmable to implement user-defined logic operations (that is, a user's circuit design). PLD pins are typically connected to the logic elements and interconnect resources through user programmable input/output (I/O) interface circuits.
FIG. 1 is a diagram showing a portion of a PLD that includes a known I/O circuit 100 connected to a pin 160 of the PLD. FIG. 1 also shows an electrostatic discharge (ESD) protection circuit 180 that is connected between ground and a node 165, which is located on a path on which signals are passed between pin 160 and I/O circuit 100.
I/O circuit 100 operates in either an input mode or an output mode in accordance with an output enable (OE) signal that is generated by the internal logic circuitry or transmitted on a global bus line of the PLD. The OE signal is provided to the first input terminal of a two-input NAND gate 110, and is inverted by an inverter 120 and applied to the first input terminal of a two-input NOR gate 130.
I/O circuit 100 also receives data output (DATA OUT) signals from internal circuitry of the PLD. The DATA OUT signals are provided to the second input terminals of NAND gate 110 and NOR gate 130. The output signal from NAND gate 110 is transmitted to the gate of a PMOS pull-up transistor 140 that is connected between Vcc and pin 160. The output signal from NOR gate 130 is transmitted to the gate of an NMOS pull-down transistor 150 that is connected between pin 160 and ground. In the output mode, a high OE signal causes pull-up transistor 140 and pull-down transistor 150 to generate high (Vcc) or low (0V or ground) signals on pin 160 in response to DATA OUT signals. In the input mode, signals received on pin 160 are transmitted through an input buffer 170, which includes serially-connected inverters 172 and 174, to a DATA IN line that transmits data input signals to the internal circuitry of the PLD.
ESD protection circuit 180 is provided to protect I/O circuit 100 from electrostatic discharge generated on pin 160 during shipping and handling of the host PLD. ESD protection circuit 180 typically includes one or more ESD protection devices that transmit these voltage pulses to ground, thereby protecting I/O circuit 100 from damage. As shown in FIG. 1, one such ESD protection device is a Silicon Controlled Rectifier (SCR) 200.
SCRs, also known as thyristors, are devices that are used extensively in power IC device applications because of their ability to switch from a very high impedance state to a very low impedance state. For the same reason, SCRs can also be used as very efficient ESD protection devices. Specifically, SCRs can conduct large currents at relatively low voltages, so the power dissipated (and resulting heat generation) is relatively low. Further, SCRs are recognized as being highly reliable in ESD protection device applications.
FIG. 2 shows SCR 200 that is implemented as an ESD protection device in ESD protection circuit 180 (see FIG. 1). SCR 200 includes a first resistance element 210, a pnp transistor 220, a npn transistor 230 and a second resistance element 240. First resistance element 210 has a first terminal connected to node 165 (see FIG. 1), and a second terminal connected to both the base of pnp transistor 220 and to the collector of npn transistor 230. The emitter of pnp transistor 220 is connected to node 165, and the collector of pnp transistor 220 is connected to both the base of npn transistor 230 and a first terminal of second resistance element 240. The emitter of npn transistor 230 and a second terminal of second resistance element 240 are connected to ground.
FIG. 3 is a cross-sectional side view showing an embodiment of SCR 200 as it is implemented on a p-type substrate 310 according to known CMOS techniques. First resistance element 210 and pnp transistor 220 are implemented in an n-well region 320 formed in p-substrate 310 by a first n+ region 322 and a first p+ region 324. Npn transistor 230 and second resistance element 240 are implemented in p-substrate 310 by a second n+ region 312 and a second p+ region 314, and by a third n+ region that extends from p-substrate 310 into n-well region 320. Node 165 is connected to first n+ region 322 and first p+ region 324. Second n+ region 312 and second p+ region 314 are connected to ground (as is p-substrate 310).
FIG. 4 shows an I-V curve that illustrates the operation of SCR 200. SCR 200 is initially in an unlatched (i.e., open circuit) state. When an ESD event occurs and a voltage pulse equal to or greater than the trigger voltage (V.sub.TRIG) is applied to pin 160, SCR 200 is triggered (turned on), thereby protecting I/O circuit 100 by clamping node 165 to a holding voltage (V.sub.HOLD), which is less than V.sub.TRIG. In particular, when a voltage level at node 165 is equal to or exceeds V.sub.TRIG, the collector-base junction of npn transistor 230 begins to leak (break down). The resulting current flow through second resistor element 240 forward biases the base-emitter junction of npn transistor 230, thereby turning on npn transistor 230. With npn transistor 230 turned on, the current passing through first resistor 210 and npn transistor 230 causes the base voltage of pnp transistor 220 to drop, thereby forward biasing the base-emitter junction and turning on pnp transistor 220. The current through pnp transistor 220 and second resistance element 240 provides a positive feedback to further turn on npn transistor 230, thereby latching SCR 200. When latched, the voltage across SCR 200 drops to V.sub.HOLD, thereby conducting large currents (i.e., significantly greater than the trigger current I.sub.TRIG) to ground. SCR 200 remains latched until the voltage at pin 160 drops to approximately V.sub.HOLD (e.g., 2 to 5 volts), at which time pnp transistor 220 and npn transistor 230 turn off, thereby unlatching SCR 200.
A problem associated with the use of SCR 200 in ESD protection circuit 180 arises during normal operation of the host PLD (i.e., after power is supplied to the host PLD). During normal operation, signals applied to pin 160 are typically between zero and five volts. However, occasional voltage spikes (i.e., above the normal signal voltage levels) may be applied to pins 160 during operation. If the voltage spike is above V.sub.TRIG (for example, 7 to 9 volts), SCR 200 is triggered and the energy of the voltage spike is routed to ground, thereby providing the beneficial effect of preventing the voltage spike from damaging, for example, I/O circuit 100 (see FIG. 1). However, unlike ESD events, the voltage on pin 160 may not drop below V.sub.HOLD after the voltage spike ends (e.g., pin 160 may be maintained at 5 volts after the voltage spike). This creates a problem in that SCR 200 remains latched after the voltage spike, and the steady-state signal intended for I/O circuit 100 is instead sunk to ground, thereby potentially causing the PLD to malfunction. Because of this potential problem, SCRs are not widely utilized by circuit designers as ESD protection devices.
What is needed is an improved SCR that reliably triggers to provide ESD protection during non-operation of a host IC device, and reliably switches off after a voltage spike during operation of the IC device, thereby avoiding the above-mentioned problem associated with known SCRs.